This invention relates to methods for fabricating transistors, namely complementary metal-oxide field effect transistors (CMOS FETS).
The cost and yield of a fabricating process for fabricating semiconductor chips depends on various factors. One factor is the number of masks (or masking layers) which are used during the process. An increase in the number of masks used in a process generally increases the cost of the process. Another factor is the extent to which the process uses self-aligned processing steps or misalignment tolerant structures. Misalignment tolerant structures are structures which, when being fabricated, have a high degree of tolerance to being misaligned with previously formed or subsequently formed structures. As is obvious, self-aligned steps or misalignment tolerant structures increase the yield of the fabricating process by reducing the number of chips which are inoperative due to misalignment. Therefore, it is generally preferable to reduce the number of masks and to increase the number of self-aligned steps and misalignment tolerant structures used in a manufacturing process. However, these two objectives must also be balanced against one another and against the features desired in a process.
Consider an exemplary DRAM memory chip. In such a DRAM memory chip, various types of logic circuits provide various functions. For example, address decoders decode address lines and access DRAM cells in a memory array, clock generators generate and process various clock signals, and refresher circuits refresh the DRAM cells in the memory array. Unlike the DRAM cells in the memory array which are implemented by a single type of metal oxide semiconductor field effect transistor (MOSFET or FET), the logic circuits in such a DRAM memory chip are typically implemented by complementary MOS FETs (CMOS FETs), which include both n-type and p-type FETs (n-FET or p-FET, respectively).
One desirable feature in a CMOS circuit is for the circuit to be a dual work function circuit. In such a circuit, the gate electrode of the n-FET transistors and the p-FET transistors are fabricated differently from one another so that they may be optimized for low work function. Since a transistor with lesser work function uses a lower voltage level than one with a higher work function, the former transistor uses lower power and may be fabricated to have smaller dimensions and faster switching speeds.
To understand such a dual work function circuit, consider an n-FET or p-FET transistor. As is well known, the gate electrode of such a transistor is made up of at least a gate oxide and a gate conductor. The gate conductor is typically a doped poly-crystalline silicon (also known as polysilicon) layer. If the gate poly-crystalline silicon layer of an n-FET or p-FET is doped with the opposite type of dopant as the channel region below the gate electrode, the work function of the gate is less than when the gate poly-crystalline silicon layer is doped with the same type of dopant. However, the channel region of a CMOS transistor may be either n-doped or p-doped silicon based on whether the CMOS transistor is a p-FET or n-FET. Therefore, to provide for optimal work function in a CMOS circuit, the gate poly-crystalline silicon layer of n-FETs should be n-doped while the gate poly-crystalline silicon layer of p-FETs should be p-doped. Such a CMOS circuit then provides for dual-work functions.
Another desirable feature in integrated circuits is the ability to use so-called "border-less" contacts, since borderless contacts have a higher degree of misalignment tolerance and allow an increased number of transistors per unit of area. Borderless contacts also reduce the possibility of a short circuit between the contact and the gate electrode. To form borderless contacts, the gate electrode is covered, in its relevant parts, by dielectric barriers. The dielectric barriers are typically a dielectric cap on the top surface of the gate electrode and dielectric spacers on the sides of the gate electrode where the contact is to be formed. Because these dielectric barriers insulate the gate electrode, there is a low probability of misalignments causing short circuits between the contact and the gate electrode.